IC62LV256 Datasheet, PDF (7/9 Pages) Integrated Circuit Solution Inc – 32K x 8 Low Power SRAM with 3.3V

IC62LV256
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2,3) (Over Operating Range)
Symbol
Parameter
-45 ns
-70 ns
-100 ns
Min. Max.
Min. Max.
Min. Max.
Unit
tWC
Write Cycle Time
tSCE
CE to Write End
45 —
70 —
100 —
ns
35 —
60 —
80 —
ns
tAW
Address Setup Time to Write End
25 —
60 —
80 —
ns
tHA
Address Hold from Write End
0—
0—
0—
ns
tSA
tPWE⁽⁴⁾
Address Setup Time
WE Pulse Width
0—
0—
0—
ns
25 —
55 —
60 —
ns
tSD
Data Setup to Write End
20 —
30 —
35 —
ns
tHD
Data Hold from Write End
0—
0—
0—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)^(1,2)
ADDRESS
CE
WE
DOUT
DIN
tWC
tSCE
tHA
tAW
tPWE
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Integrated Circuit Solution Inc.
7
ALSR007-0A 10/5/2001