IC62LV256 Datasheet, PDF (3/9 Pages) Integrated Circuit Solution Inc – 32K x 8 Low Power SRAM with 3.3V

IC62LV256
PIN CONFIGURATION
28-Pin DIP, SOJ and SOP
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
OE 22
A11 23
A9 24
A8 25
A13 26
WE 27
VCC 28
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A0
9 A1
8 A2
PIN DESCRIPTIONS
A0-A14
CE
OE
WE
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE CE OE I/O Operation Vcc Current
XHX
High-Z
ISB1, ISB2
HLH
HL L
LLX
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
Unit
–0.5 to +4.6
V
–55 to +125
°C
–65 to +150
°C
0.5
W
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Integrated Circuit Solution Inc.
3
ALSR007-0A 10/5/2001