IC62LV12816DL Datasheet, PDF (8/12 Pages) Integrated Circuit Solution Inc – 128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

IC62LV12816DL
IC62LV12816DLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
-55
-70
-100
Min. Max.
Min. Max.
Min. Max
Unit
tWC Write Cycle Time
55 —
70 —
100 —
ns
tSCE CE1 Low and CE2 HIGH to Write End 50 —
65 —
80 —
ns
tAW Address Setup Time to Write End
50 —
65 —
80 —
ns
tHA Address Hold from Write End
0—
0—
0—
ns
tSA Address Setup Time
tPWB LB, UB Valid to End of Write
tPWE WE Pulse Width
0—
0—
0—
ns
45 —
60 —
80 —
ns
45 —
40 —
80 —
ns
tSD Data Setup to Write End
25 —
30 —
40 —
ns
tHD
tHZWE⁽³⁾
tLZWE⁽³⁾
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0—
0—
0—
ns
— 30
— 30
— 40
ns
5—
5—
5—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, and UB or LB, WE LOW, and CE2 HIGH. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1^(1,2) (CE1 or CE2, Controlled, OE = HIGH or LOW)
ADDRESS
t SA
CE1
t WC
VALID ADDRESS
t SCE
t HA
CE2
WE
UB, LB
DOUT
DIN
t AW
t PWE
t PBW
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the WE, CE1 = VIL, CE2 = VIH and at least one of the LB
and UB inputs being in the LOW state.
8
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002