IC62C1024AL Datasheet, PDF (7/9 Pages) Integrated Circuit Solution Inc – 128K x 8 Low Power CMOS SRAM

IC62C1024AL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range, Standard and Low
Power)
Symbol Parameter
-35
Min. Max.
-45
Min. Max.
-55
Min. Max.
-70
Min. Max. Unit
tWC Write Cycle Time
tSCE1 CE1 to Write End
35 —
25 —
45 —
35 —
55 —
50 —
70 —
ns
60 —
ns
tSCE2 CE2 to Write End
25 —
35 —
50 —
60 —
ns
tAW Address Setup Time to Write End 25 —
35 —
45 —
60 —
ns
tHA Address Hold from Write End
0—
0—
0—
0—
ns
tSA Address Setup Time
tPWE⁽⁴⁾ WE Pulse Width
0—
25 —
0—
35 —
0—
40 —
0—
ns
50 —
ns
tSD Data Setup to Write End
20 —
25 —
25 —
30 —
ns
tHD Data Hold from Write End
tHZWE⁽²⁾ WE LOW to High-Z Output
tLZWE⁽²⁾ WE HIGH to Low-Z Output
0—
— 10
3—
0—
— 15
5—
0—
— 20
5—
0—
ns
— 25
ns
5—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)^(1,2)
ADDRESS
CE1
CE2
WE
DOUT
DIN
tWC
tSCE1
tHA
tSCE2
tAW
tPWE⁽⁴⁾
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Integrated Circuit Solution Inc.
7
ALSR009-0A 5/7/2002