IC61S25632T Datasheet, PDF (7/22 Pages) Integrated Circuit Solution Inc – 8Mb SyncBurst Pipelined SRAM

IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
256K x 36
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa -BWd
BWE
GW
CE,CE2,CE2
OE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQd
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
DQPa-DQPd
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
Parity Data I/O
Integrated Circuit Solution Inc.
7
SSR014-0B 08/13/2002