IC61S25632T Datasheet, PDF (14/22 Pages) Integrated Circuit Solution Inc – 8Mb SyncBurst Pipelined SRAM

IC61S25632T/D IC61S25636T/D
IC61S51218T/D
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-250
-200
-166
-133
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
4 — 5 — 6 — 7.5 — ns
Pipeline tKQ
Clock Access Time
— 3 — 3.1 — 3.5 — 4 ns
tKQX⁽¹⁾ Clock High to Output Invalid
1.0 — 1.0 — 1.5 — 1.5 — ns
tKQLZ^(1,2) Clock High to Output Low-Z
0 — 0 — 0 — 0 — ns
tKH
Clock High Pulse Width
1.6 — 2 — 2.3 — 2.8 — ns
tKL
Clock Low Pulse Width
1.6 — 2 — 2.3 — 2.8 — ns
tKQHZ^(1,2) Clock High to Output High-Z
— 3.1 — 3.1 — 3.5 — 4 ns
tOEQ
Output Enable to Output Valid
— 3.1 — 3.1 — 3.5 — 4 ns
tOELZ^(1,2) Output Enable to Output Low-Z
0 — 0 — 0 — 0 — ns
tOEHZ^(1,2) Output Enable to Output High-Z
— 3.0 — 3.0 — 3.5 — 4 ns
tAS
Address Setup Time
1.5 — 1.5 — 1.5 — 1.5 — ns
tSS
Address Status Setup Time
1.5 — 1.5 — 1.5 — 1.5 — ns
tWS
Write Setup Time
1.5 — 1.5 — 1.5 — 1.5 — ns
tCES
Chip Enable Setup Time
1.5 — 1.5 — 1.5 — 1.5 — ns
tAVS
Address Advance Setup Time
1.5 — 1.5 — 1.5 — 1.5 — ns
tDS
Data Setup time
1.5 — 1.5 — 1.5 — 1.5 — ns
tDH
Data Hold time
0.5 — 0.5 — 0.5 — 0.5 — ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 — ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 — ns
tWH
Write Hold Time
0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH
Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH
Address Advance Hold Time
0.5 — 0.5 — 0.5 — 0.5 — ns
tZZS
ZZ Setup Time
2 — 2 — 2 — 2 — cyc
tZZREC ZZ Recovery Time
2 — 2 — 2 — 2 — cyc
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002