IC61S25632T Datasheet, PDF (18/22 Pages) Integrated Circuit Solution Inc – 8Mb SyncBurst Pipelined SRAM

IC61S25632T/D IC61S25636T/D
IC61S51218T/D
READ/WRITE CYCLE TIMING: PIPELINED
CLK
ADSP
ADSC
tKC
tKH
tKL
tSS
tSH
tSS
tSH
ADSP is blocked by CE1 inactive
ADV
Addresses
GW
BWE
BW4-BW1
CE
CE2
CE2
OE
DATAOUT
DATAIN
tAS
tAH
RD1
WR1
RD2
tWS
tWH
tWS
tWH
tCES
tCEH
tWS
tWH
WR1
CE1 Masks ADSP
tCES
tCEH
tCES
tCEH
tOEQ
CE2 and CE3 only sampled with ADSP or ADSC
tOEHZ
High-Z
High-Z
tOELZ
tKQLZ
tKQ
Single Read
tOEQX
1a
tKQX
tKQHZ
1a
tDS
tDH
Single Write
2a
2b
2c
Burst Read
RD3
Unselected with CE3
tKQX
2d
tKQHZ
Unselected
18
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002