IC41C16256 Datasheet, PDF (7/21 Pages) Integrated Circuit Solution Inc – 256Kx16 bit Dynamic RAM with EDO Page Mode

IC41C16256
IC41LV16256
ELECTRICAL CHARACTERISTICS⁽¹⁾
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL
Input Leakage Current
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
–10 10 µA
IIO
Output Leakage Current
Output is disabled (Hi-Z)
0V < VOUT < Vcc
–10 10 µA
VOH
Output High Voltage Level
IOH = –2.5 mA
2.4 —
V
VOL
Output Low Voltage Level
IOL =+2.1mA
— 0.4
V
ICC1
Standby Current: TTL
RAS, LCAS, UCAS > VIH Commerical 5V
—
Industrial
5V
—
Commerical 3.3V —
Industrial 3.3V —
2
mA
3
1
2
ICC2
Standby Current: CMOS
RAS, LCAS, UCAS > VCC – 0.2V
5V
—
3.3V —
1
mA
0.5
ICC3
Operating Current:
RAS, LCAS, UCAS,
Random Read/Write^(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
-25 — 260 mA
-35 — 230
-50 — 180
-60 — 170
ICC4
Operating Current:
RAS = VIL, LCAS, UCAS,
EDO Page Mode^(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-25 — 250 mA
-35 — 220
-50 — 170
-60 — 160
ICC5
Refresh Current:
RAS Cycling, LCAS, UCAS > VIH
RAS-Only^(2,3)
tRC = tRC (min.)
Average Power Supply Current
-25 — 260 mA
-35 — 230
-50 — 180
-60 — 170
ICC6
Refresh Current:
RAS, LCAS, UCAS Cycling
CBR^(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-25 — 260 mA
-35 — 230
-50 — 180
-60 — 170
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
7
DR018-0C 04/23/2004