IC62C1024L Datasheet, PDF (6/8 Pages) Integrated Circuit Solution Inc – 128K X 8 LOW POWER CMOS STATIC RAM

IC62C1024L
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range, Standard and Low
Power)
Symbol Parameter
tWC Write Cycle Time
tSCE CE1 to Write End
tSCE CE2 to Write End
tAW Address Setup Time to Write End
tHA Address Hold from Write End
tSA Address Setup Time
tPWE^" WE Pulse Width
tSD Data Setup to Write End
tHD Data Hold from Write End
tHZWE WE LOW to High-Z Output
tLZWE WE HIGH to Low-Z Output
-35
Min. Max.
35 —
25 —
25 —
25 —
0—
0—
25 —
20 —
0—
— 10
3—
-45
Min. Max.
45 —
35 —
35 —
35 —
0—
0—
35 —
25 —
0—
— 15
5—
-55
Min. Max.
55 —
50 —
50 —
45 —
0—
0—
40 —
25 —
0—
— 20
5—
-70
Min. Max. Unit
70 —
ns
60 —
ns
60 —
ns
60 —
ns
0—
ns
0—
ns
50 —
ns
30 —
ns
0—
ns
— 25
ns
5—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in .igure 1a.
2. Tested with the load in .igure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVE.ORMS
WRITE CYCLE NO. 1 (9- Controlled)^(1,2)
ADDRESS
CE1
CE2
WE
DOUT
DIN
tWC
tSCE1
tHA
tSCE2
tAW
tPWE⁽⁴⁾
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
6
Integrated Circuit Solution Inc.
ALSR006-0A