IC89E54 Datasheet, PDF (22/36 Pages) Integrated Circuit Solution Inc – 8-BITS SINGLE MICROCONTROLLER with 16/32/64-Kbytes of FLASH, 256 byte +512 byte RAM

IC89E54/58/64
Arming Command
An arming command must take place before a Written Mode will be recognized by the IC89E54/58/64. This is to prevent
accidental triggering of written operation due to noise or programmer error. The arming command is as follows:
A Read Signature Bytes command is issued. This is actually a natural step for the programmer, but will also serve as
the arming command. After the above sequence, all other Written Mode commands are enabled. Before the Read Signature
Bytes command is received, all other Written Mode commands received are ignored. The IC89E54/8/64 will exit Written
Mode if power off, so arming command is needed every power on for entering External Host Command Mode.
External Host Mode Commands
The following is a brief description of the commands. See Table 4 for all signal logic assignments for the External Host
Mode Commands. The critical timing for all Erase and Program commands, is self-generated by the flash memory controller
on-chip.
The high-to-low transition of the PROG signal initiates the Erase and Program commands, which are synchronized
internally. All the data in the memory array will be erased to FFH. Memory addresses that are to be programmed must be
in the erased state prior to programming. Selection of the Erase command to use, prior to programming the device, will be
dependent upon the contents already in the array and the desired programming field block.
The “Chip Erase” command erases all bytes in both memory blocks of the IC89E54/58/64.This command ignores the
“Lock bits” status and will erase the Security Byte. The “Chip Erase” command is selected by the byte code of 01H on P3
[7:6] and P2[7:6].
Flash Operation Status Detection (Ext. Host Handshake)
The IC89E54/58/64 provide two signals mean for an external host to detect the completion of a flash memory
operation, therefore the external host can optimize the system Program or Erase cycle of the embedded flash memory.
The end of a flash memory operation cycle (Erase or Program) can be detected by monitoring the Ready/Busy bit at
Port 3.4. The following two Program commands are for programming new data into the memory array. Selection of
which Program command to use for programming will be dependent upon the desired programming field size. The
Program commands will not enable if the Lock bit 2 or Lock Bit 3 is enabled on the selected memory block. The
“Program Main Code” command program data into a single byte. Ports P0[0:7] are used for data in. The memory
location is selected by P1[0:7], P2[0:5], and P3[2:3] (A0-A15). The “Program Main Code” command is selected by the
byte code on P3[6:7] and P2[6:7].
The “Verify Main Code” command allows the user to verify that the IC89E54/58/64 correctly performed an Erase or
Program command. Ports P0[0:7] are used for data out. The memory location is selected by P1[0:7], P2[0:5], and P3[2:3]
(A0-A15). These commands will not enable if any lock bit is enabled on the selected memory block.
Ready/Busy
The progress of the flash memory programming can be monitored by the Ready/Busy output signal. The Ready/Busy
indicates whether an Embedded Algorithm in Written State Machine (WSM) is in progress or complete. The RY/BY status
is valid after the falling edge of the programming or erase controlled signal. If the output is low (Busy), the device is in an
erasing/programming state with an internal verification. If the output is high, the device is ready to read data. If Ready/Busy
signal doesn’t generate a low pulse or doesn’t return from low to high in an expected time, the programming/erasing action
will be failed.
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Integrated C ircuitSolution Inc.
MC012-0C 11/16/2001