X84160 Datasheet, PDF (6/22 Pages) IC MICROSYSTEMS – Advanced MPS™ Micro Port Saver EEPROM with Block Lock™ Protection

X84160/640/128
Low Power Operation
—A reset sequence must be issued to set the internal
The device enters an idle state, which draws minimal cur-
write enable latch before starting a write sequence.
rent when:
—A special “start nonvolatile write” command sequence
—an illegal sequence is entered. The following are the
more common illegal sequences:
• Read/Write/Write—any time
• Read/Write ‘1’—When writing the address or
writing data.
• Write ‘1’—when reading data
• Read/Read/Write ‘1’—after data is written to
device, but before entering the NV write sequence.
—the device powers-up;
—a nonvolatile write operation completes.
While a sequential read is in progress, the device
remains in an active state. This state draws more current
than the idle state, but not as much as during a read
itself. To go back to the lowest power condition, an invalid
condition is created by writing a ‘1’ after the last bit of a
read operation.
is required to start a nonvolatile write cycle.
—The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
t _{—The internal Write Enable latch is reset and remains}
reset as long as the WP pin is LOW, which blocks all
c nonvolatile write cycles.
—The internal Write Enable latch resets on an invalid
u ^{write operation.}
SYMBOL TABLE
d _{WAVEFORM INPUTS}
OUTPUTS
oMust be
steady
Will be
steady
r May change
from LOW to
HIGH
P ^{May change}
Will change
from LOW to
HIGH
Will change
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
e _{—The internal Write Enable latch is reset upon}
Obsolet ^power-up.
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
from HIGH to
LOW
Changing:
State Not
Known
Center Line
is High
Impedance
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