X84160 Datasheet, PDF (5/22 Pages) IC MICROSYSTEMS – Advanced MPS™ Micro Port Saver EEPROM with Block Lock™ Protection

X84160/640/128
CONTROL REGISTER
The Write Protect (WP) pin and the nonvolatile Write
The X84160/640/128 has one register that contains
control bits for the devices. The control bits, WPEN, BP1,
and BP0, are shown in Table 1. To read or change the
contents of this register requires a one byte operation to
address FFFFh.
A read from FFFFh returns the one byte contents of the
control register unused bits return 0. Continued reads
return undefined data. A write to address FFFFh changes
the value of the bits. Unused bits are written as “0”.
Writing more than one byte to the control register is a
violation and the operation will be aborted. After sending
one byte to the control register, a start nonvolatile write
cycle will latch in the new state.
Table 1
7
654 3
2
10
WPEN 0 0 0 BP1 BP0 0 0
WPEN: Write Protect Enable Bit
The Write-Protect-Enable (WPEN) bit is an enable bit for
Protect Enable (WPEN) bit in the Status Register control
the programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
LOW, and the WPEN bit is “1”. Hardware write protection
is disabled when either the WP pin is HIGH or the WPEN
bit is “0”. When the chip is hardware write protected,
t nonvolatile write is disabled to the Control Register,
including the Block Protect bits and the WPEN bit itself,
as well as the block-protected sections in the memory
c _{array. Only the sections of the memory array that are not}
block-protected can be written.
u Note: When the WP pin is tied to VSS and the WPEN bit is HIGH, the
WPEN bit is write protected. It cannot be changed back to a
“0”, as long as the WP pin is held LOW.
d _{BP1, BP0: Block Protect Bits}
The Block Protect (BP0 and BP1) bits are nonvolatile and
o ^{allow the user to select one of four levels of protection.}
The X84160/640/128 is divided into four segments. One,
r two, or all four of the segments may be protected. That is,
the user may read the segments but will be unable to
P^{alter (write) data within the selected segments. The}
the WP pin.
Table 2
WPEN
e ₀
t ₁
X
WP
X
LOW
HIGH
Protected
Blocks
Protected
Protected
Protected
Unprotected
Blocks
Writable
Writable
Writable
Status
Register
Writable
Protected
Writable
partitioning is controlled as illustrated in table 3 below.
le _{Table 3. Block Lock Protection}
o _{Control Register Bits}
BP1
BP0
s ₀
0
0
1
b ₁
0
X84160
None
0600h–07FFh
0400h–07FFh
O¹
1
0000–07FFh
Array Address Protected
X84640
X84128
None
None
1800h–1FFFh 3000h–3FFFh
1000h–1FFFh 2000h–3FFFh
0000–1FFFh
0000h–3FFFh
Array
upper 1/4
upper 1/2
Full Array
(Not including the
control register.)
5