X84160 Datasheet, PDF (2/22 Pages) IC MICROSYSTEMS – Advanced MPS™ Micro Port Saver EEPROM with Block Lock™ Protection

X84160/640/128
PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches:
8-LEAD PDIP
8-LEAD SOIC
8-LEAD TSSOP
PIN NAMES
CE
I/O
WP
VSS
1
8
2 _X84160 7
3 X84640 ⁶
4
5
.230 in.
VCC
NC
OE ^{.190 in.}
NC
V_CC
CE
I/O
WE
CE
I/O
NC
NC
NC
WP
VSS
14-LEAD SOIC
1
14
2
13
3
12
4
11
X84128
5
10
6
9
7
8
NC
V _CC
NC
CE
NC
I/O
NC
NC
NC
NC
NC
NC ^{.390 in. WP}
OE
VSS
NC
WE
.230 in.
NC
NC
CE
8-LEAD XBGA: Top View
CE
CE
I/O
VCC _{1 8} I/O
NC
NC
NC 2 7 CE
NC
WP
1
8
2
3
X84160
7
6
4
5
.252 in.
20-LEAD TSSOP
1
20
2
19
3
18
4
17
5
X84640
16
6
15
7
14
8
13
9
12
10
11
.252 in.
28-LEAD TSSOP
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
X84128
21
9
20
10
19
OE
WE _{.114 in.}
WP
VSS
t _NC
NC
c ^VCC
NC
NC
NC
.250 in.
u ^NC
OE
WE
NC
d _NC
o NC
NC
NC
r^VCC
NC
NC
NC
.394 in.
NC
P^OE
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
V_CC Supply Voltage
V_SS Ground
NC No Connect
PACKAGE
SELECTION GUIDE
8-Lead PDIP
84160 8-Lead SOIC
8-Lead TSSOP
84640
8-Lead CSP/BGA
8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP
WE ^{3 6 VSS}
OE 4 ⁵ WP
e ^{.078 in.}
V_SS
11
NC
12
NC
13
NC
14
18
WE
17
NC
16
NC
15
NC
. 252 in.
84128
8-Lead CSP/BGA
8-Lead PDIP
14-Lead SOIC
28-Lead TSSOP
t ^{PIN DESCRIPTIONS}
Chip Enable (CE)
e ^{The Chip Enable input must be LOW to enable all read/}
write operations. When CE is HIGH, the chip is dese-
l _{lected, the I/O pin is in the high impedance state, and}
unless a nonvolatile write operation is underway, the
o ^{device is in the standby power mode.}
Output Enable (OE)
s ^{The Output Enable input must be LOW to enable the out-}
put buffer and to read data from the device on the I/O line.
b ^{Write Enable (WE)}
The Write Enable input must be LOW to write either data
O ^{or command sequences to the device.}
Write Protect (WP)
The Write Protect input controls the Hardware Write Pro-
tect feature. When WP is LOW and the nonvoltaile bit
WPEN is “1”, nonvolatile writes of the X84160/640/128
control register is disabled, but the part otherwise func-
tions normally. When WP is held HIGH, all functions,
including nonvolatile write operate normally. WP going
LOW while CS is still LOW will interrupt a write to the
X84160/640/128 control register. If the internal Write
cycle has already been initiated, WP going LOW will
have no effect on write.
The WP pin function is blocked when the WPEN bit in the
control register is “0”. This allows the user to install the
X84160/640/128 in a system with WP pin grounded and
still be able to write to the control register. The WP pin
Data In/Data Out (I/O)
functions will be enabled when the WPEN bit is set “1”.
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
2