X25642 Datasheet, PDF (2/16 Pages) Xicor Inc. – Advanced SPI Serial E 2 PROM with Block Lock TM Protection

X25642
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25642 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25642 will be
in the standby power mode. CS LOW enables the
X25642, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25642 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including
nonvolatile writes operate normally. WP going LOW
while CS is still LOW will interrupt a write to the
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
V_SS
V_CC
HOLD
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
7037 FRM T01
X25642 status register. If the internal write cycle has
already been initiated, WP going LOW will have no
affect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25642 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
PIN CONFIGURATION
SOIC/DIP
Not to Scale
CS
.197" ^SO
SOIC
Only
WP
VSS
1
8
2
7
X25642
3
6
4
5
VCC
HOLD
SCK
SI
.244"
SOIC
NC
CS*
CS*
.345"
SO
WP
VSS
NC
1
14
2
13
3
12
4 X25642 11
5
10
6
9
7
8
NC
NC
VCC
HOLD
SCK
SI
NC
.244"
NC
CS
NC
SO
NC
.300"
NC
WP
VSS
NC
NC
TSSOP
1
2200
2
1199
3
1188
4
1177
5
1166
6 ^X25642 1155
7
1144
8
1133
9
1122
10
1111
NC
VCC
NC
HOLD
NC
NC
SCK
SI
NC
NC
.252"
3132 ILL F02.5
* Pin 2 and Pin 3 are internally connected. Only one CS needs to
be connected externally.
2