IC-TW8_13 Datasheet, PDF (8/63 Pages) IC-Haus GmbH – 16-BIT SIN/COS INTERPOLATOR WITH AUTO-CALIBRATION

iC-TW8 16-BIT SIN/COS
WITH AUTO-CALIBRATION
INTERPOLATO_pR_reliminary
Rev A2, Page 8/12
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = 3.1...5.5 V, Tj = -40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter
No.
Conditions
Unit
Min. Typ. Max.
Total Device
001 AVDD,
DVDD
Permissable Supply Voltage
AVDD, DVDD
3.1
5.5
V
002 IDD
Total Supply Current in AVDD fin = 1 kHz, Increments 4096, Post-AB Divider
and DVDD
1, error-free boot-up from EEPROM;
VDD = 5 V, 32 MHz crystal
25
mA
VDD = 3.3 V, 20 MHz crystal
12
mA
Signal Inputs and Amplifiers: SIN+, SIN-, COS+, COS-
101 Vin()
Permissible Input Voltage
1.4
AVDD - V
1.0
102 Vos()
Amplifier Input Offset Voltage
±12 mV
103 Iin()
Input Leakage Current
±50 nA
105 OFFcorr Correctable Input Offset Voltage as percentage of input signal amplitude; input ±100
%
offset voltage is the sum of sensor offset plus
amplifier offset (item 102);
106 Acorr
Correctable SIN/COS Amplitude max(Asin, Acos) / min(Asin, Acos), whereas
1.24
Mismatch
Asin and Acos are the SIN/COS input ampli-
tudes respectively.
107 PHIcorr
Correctable SIN/COS Phase
Error
(step size 0.052 degree)
±53
deg
108 Rpu()
Pull-Up Resistor at SIN+, COS+ MAIN_CFG.pull = 1
2
MΩ
109 Rpd()
Pull-Down Resistor at SIN-, COS- MAIN_CFG.pull = 1
Index Signal Inputs and Amplifier: ZERO+, ZERO-
201 Vin()
Permissible Input Voltage
0
202 Vos()
Input Referred Offset Voltage
203 Iin()
Input Leakage Current
Converter Performance
301 INL
Integral Nonlinearity
refer to Figure 2, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
302 DNL
Differential Nonlinearity
refer to Figure 2, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
303 N
Output Angle Noise
1 Vpp-diff SIN/COS input, fin = 0 Hz
Clock: XIN, XOUT
401 fxtl
Permissible External Frequency AVDD, DVDD = 5 V
6
driven into XOUT
AVDD, DVDD = 3.3 V
6
402 fosc
Internal Oscillator Frequency
Tj = 27 °C, MAIN_CLOCK.freq = 0;
AVDD, DVDD = 3.3 V
AVDD, DVDD = 5 V
Reset and Start-Up: xRST
601 DVDDon DVDD Reset Threshold
increasing voltage at DVDD;
xRST tied to DVDD
xRST connected through 68 kΩ to DVSS
602 Vt()hi
Input Logic Threshold High
603 Vt()lo
Input Logic Threshold Low
0.8
604 Rpu()
Pull-Up Resistor
V() = 0 ... DVDD - 1 V
605 tstart
Startup Time
AVDD, DVDD = 5 V, fxtl = 24 MHz by crystal;
pin configuration (EEPROM connected)
ready for serial config. (EEPROM connected)
ready for serial config. (no EEPROM)
2
MΩ
AVDD V
±12 mV
±50 nA
0.08 deg
0.02 deg
0.08 deg
32 MHz
24 MHz
16
MHz
20
MHz
2.7
V
4.0
V
2.2
V
V
40
kΩ
100
ms
100
ms
tbd.
ms