IC-PMX Datasheet, PDF (22/27 Pages) IC-Haus GmbH – ENERGY HARVESTING MULTITURN COUNTER/ENCODER

iC-PMX
ENERGY HARVESTING MULTITURN COUNTER/ENCODER
Rev A3, Page 22/27
Position Data in Period Counter Mode with a standard FRAM
The revolution counter register maps for use with a standard FRAM are optimized against imprint effects of FRAM.
This is realized by balancing the 0/1 duty cycle of the POS bits: The POS value is inverted if LPP is high, the POS
bit length is coded in Bit 1 and Bit 0 of address 0x0.
16 Bit Revolution Counter Register Map
Addr
Bit 7
Bit 6
Bit 5
0x00
POS(3:0)
0x01
0x02
CRC(3:0)
0x03
...
0x0E
0x0F
—
Bit 4
Bit 3
LPP
POS(11:4)
—
INVALID
C3
Bit 2
LMP
Bit 1
0
POS(15:12)
C2
C1
Bit 0
0
C0
Table 17: 16 Bit Revolution Counter Register Map
24 Bit Revolution Counter Register Map
Addr
Bit 7
Bit 6
Bit 5
0x00
POS(3:0)
0x01
0x02
0x03
CRC(3:0)
0x04
...
0x0E
0x0F
—
Bit 4
Bit 3
LPP
POS(11:4)
POS(19:12)
—
INVALID
C3
Bit 2
LMP
Bit 1
0
POS(23:20)
C2
C1
Table 18: 24 Bit Revolution Counter Register Map
Bit 0
1
C0
32 Bit Revolution Counter Register Map
Addr
Bit 7
Bit 6
Bit 5
0x00
POS(3:0)
0x01
0x02
0x03
0x04
CRC(3:0)
0x05
...
0x0E
0x0F
—
Bit 4
Bit 3
LPP
POS(11:4)
POS(19:12)
POS(27:20)
—
INVALID
C3
Bit 2
LMP
Bit 1
1
POS(31:28)
C2
C1
Table 19: 32 Bit Revolution Counter Register Map
Bit 0
0
C0