IC-LO_16 Datasheet, PDF (20/25 Pages) IC-Haus GmbH – TRIANGULATION SENSOR

iC-LO
TRIANGULATION SENSOR
preliminary
Rev B3, Page 20/25
All status bits are updated with each register access.
The exception to the rule is the ERROR bit; this bit
indicates whether an error occurred during the last SPI-
communication with the slave.
The master transmits the REGISTER status/data op-
code. The slave immediately passes the opcode on to
MISO. The slave then transmits the STATUS byte and
a DATA byte. The DATA-Byte is undefined in the actual
configuration.
NCS
SCLK
MOSI
MISO
OP
OP STATUS DATA
The master transmits the Write REGISTER (cont.) op-
code. In the second byte start address ADR is trans-
mitted, followed by the DATA1-DATAn data packets to
be written. The slave immediately outputs the opcode,
address and data at MISO. The slave increments its
internal address counter following each data packet.
If an error occurs during write to register in continuous
mode (e.g. the address is invalid or the data write pro-
cess of the last address was not finished), the internal
address counter is no longer incremented and the error
bit FAIL is set in the communication status register (see
page 20).
8 cylces
Figure 9: REGISTER status/data
Read REGISTER (cont.)
Reading data from internal registers the slave does not
need any processing time. These registers can be read
out in continous mode.
The master transmits the Read REGISTER (cont.) op-
code. In the second byte the start address ADR is
transmitted. The slave immediately outputs the opcode,
address and then transmits the DATA1 data. The inter-
nal address counter is incremented following each data
packet.
NCS
SCLK
MOSI
MISO
OP ADR DATA1 DATA2 ...
OP
ADR DATA1 DATA2 ...
8 cycles
Figure 11: Write REGISTER (cont.)
Read STATUS
If an error occurs during register readout in continuous
mode (e.g. the address is invalid or the requested data
is not yet valid on data byte clockout), the internal ad-
dress counter is no longer incremented and the error
bit FAIL is set in the communication status register (see
page 20).
NCS
SCLK
MOSI
MISO
OP ADR
OP ADR DATA1 DATA2 ...
The command Read STATUS is designed to enable a
fast readout of the internal, slave-specific status regis-
ters of a slave (STAT1-STATn). The opcode sets the
address in the slave to the lowest STAT address. The
internal address counter is incremented following each
STAT byte. This command largely corresponds to the
Read REGISTER (cont.) command, with the difference
that here the addressing sequence is missing and the
master does not need to know the slave’s exact STAT
address.
8 cycles
Figure 10: Read REGISTER (cont.)
Write REGISTER (cont.)
NCS
SCLK
MOSI
MISO
OP
OP STAT1 STAT2 ...
Writing data into internal registers the slave does not
need any processing time. These registers can be
written in continous mode.
8 cycles
Figure 12: Read STATUS