IC-GF_15 Datasheet, PDF (19/30 Pages) IC-Haus GmbH – TRANSCEIVER

iC-GF
TRANSCEIVER
SPI MODE
Rev F1, Page 19/30
In SPI mode the iC-GF is configured and operated us-
ing the on-chip registers. Additionally there is a status
register, where chip events are logged. If any of the
status bits is set to high, the low-active open-drain pin
NDIAG is activated, e.g. for interrupt generation for mi-
cro controllers. The SPI mode is activated when the
pin INV1 is left open and the filter time (cf. Electrical
Characteristic No. 614) has elapsed. This enables com-
munication with the iC-GF via an SPI protocol using
pins MISO, MOSI, SCLK and NCS. After power-up, the
output switches remain at high impedance for ca. 50 ms.
During this time, the SPI interface can be used to set
the desired output configuration.
Switch enable
There are three different ways of enabling/disabling the
output switches in SPI mode: pin mode, register mode
and mixed mode. In pin mode (TXEN = "11") or register
mode (TXEN = "00") the OEN pin acts as a common
enable for both switching channels. The OEN regis-
ter on the other hand enables or disables each switch
separately.
Switch enable
OEN pin TXEN(1:0) OEN(1:0) Qx2 Qx1
0
00/11
XX
disabled disabled
1
00/11
01
disabled enabled
1
00/11
10
enabled disabled
1
XX
11
enabled enabled
X
XX
00
disabled disabled
0
01
0X
disabled disabled
0
01
1X
enabled disabled
0
10
X0
disabled disabled
0
10
X1
disabled enabled
1
01
01
disabled enabled
1
01
10
enabled disabled
1
10
01
disabled enabled
1
10
10
enabled disabled
A "0" in the register TXEN sets the corresponding switch
to be controlled by the relevant bit of the register OUTD.
TXEN(1:0)
x0
x1
0x
1x
Addr. 0x00; bit (5:4)
Channel 1 controlled by OUTD(0)
Channel 1 controlled by TX
Channel 2 controlled by OUTD(1)
Channel 2 controlled by TX
Table 6: Transmit enable
R/W 01
OUTD(1:0)
x0
x1
0x
1x
Addr. 0x00; bit (1:0)
R/W 00
Channel 1: push-pull low resp. high/low-side off
Channel 1: push-pull high resp. high/low-side on
Channel 2: push-pull low resp. high/low-side off
Channel 2: push-pull high resp. high/low-side on
Table 7: Output data with INV = "00"
Switch configuration
The configuration of the switches is determined by the
registers QCFG1 and QCFG2; either as high-side, low-
side, push-pull or high impedance (disabled).
QCFG1(1:0)
Addr. 0x01; bit (5:4)
00
disabled
01
low-side switch
10
high-side switch
11
push-pull
R/W 11
Table 8: Switch configuration Channel 1
QCFG2(1:0)
Addr. 0x01; bit (7:6)
00
disabled
01
low-side switch
10
high-side switch
11
push-pull
R/W 11
Table 9: Switch configuration Channel 2
Table 5: Switch enable, QCFGx =/ "00"
INV inverts the corresponding switching channel.
In mixed mode (TXEN = "01" or "10") the OEN pin acts
as an enable only for the channel for which the TXEN
bit is set to "1". The OEN register enables or disables
each switching channel separately. Table 5 summarises
these configurations.
Switch control
Each switch can be operated by the OUTD register or
the input pin TX. The register TXEN selects register
OUTD or the pin TX for switch control.
INV(1:0)
x0
x1
0x
1x
Addr. 0x03; bit (5:4)
Switching channel 1 not inverted
Switching channel 1 inverted
Switching channel 2 not inverted
Switching channel 2 inverted
Table 10: Invert Ouput
R/W 00
Table 11 summarises the above configurations for chan-
nel 1.