IC-MQF Datasheet, PDF (18/37 Pages) IC-Haus GmbH – PROGRAMMABLE 12-BIT Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MQF PROGRAMMABLE 12-BIT ^preliminary
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
OPERATING MODES
Rev A1, Page 18/37
iC-MQF has various modes of operation, for which the
functions of outputs PA, NA, PB, NB, PZ, NZ and ERR
are altered.
coder quadrature signal with a zero pulse. Only in
these modes are the line drivers and the reverse po-
larity protection feature active.
Two operating modes can be selected for the out-
put of the angle position in normal operation. Mode
191/193 provides control signals for devices compati-
ble with 74HC191 or 74HC193, whereas in Mode ABZ
the angle position is output incrementally as an en-
In order to condition the input signals and to cali-
brate and test iC-MQF Calibration and Test modes
are available. Digital and analog test signals are pro-
vided; the latter must always be measured at high load
impedance.
MODE(3:0)
Code
0x00
0x0F
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Operating Mode
Mode ABZ
Mode 191/193
Calibration 1
Calibration 2
res. *
res. *
Test 5
Test 6 (MUX=0x40)
Calibration 3
res. *
res. *
res. *
System Test
res. *
res. *
res. *
Hints
Addr. 0x02; bit 3:0
Pin PA
Pin NA
Pin PB
Pin NB
A
not(A)
B
not(B)
CPD
CPU
CP
nU/D
res.
res.
res.
IBN
PCH1
NCH1
PCH2
NCH2
res.
res.
res.
res.
res.
res.
res.
res.
PSIN
NSIN
PCOS
NCOS
X4
X6
X3
X5
VTs
VTth
res.
res.
res.
res.
res.
res.
res.
res.
A₄
A₈
B₄
B₈
res.
res.
res.
res.
res.
res.
res.
res.
res.
*) Test function for iC-Haus device test only.
Pin PZ
Z
MR
PCH0
VDC1
res.
res.
res.
X1
VTTFE
res.
Z_In
res.
res.
Pin NZ
not(Z)
nPL
NCH0
VDC2
res.
res.
res.
X2
VTTSE
res.
TP1
res.
res.
Pin ERR
ERR
ERR
res.
res.
res.
res.
res.
res.
ERR
res.
ERR
res.
res.
Table 13: Operating Modes
Mode ABZ
In Mode ABZ A/B signals are generated and output via
PA, NA, PB and NB. A configurable zero signal is pro-
vided at pins PZ and NZ. The differential RS422 line
drivers are active; a Nx pin supplies a complementary
signal which is the inversion of pin Px.
Mode 191/193
In Mode 191/193 the output pins provide control sig-
nals for counter devices compatible with 74HC191 or
74HC193 according to the following table. The driving
capability (SIK) and the slew rate (SSR) of the output
drivers must be selected so that the clock pulses can
be output with a short low pulse according to the cho-
sen minimum phase distance (see Electrical Charac-
teristics, 511).
Mode 191/193
Pin Signal
PA CPD
NA CPU
PB CP
NB nU/D
PZ MR
NZ nPL
Description
Clock Down Pulse
Clock Up Pulse
Clock Pulse
Count Direction (0: up, 1: down)
Asynch. Master Reset (active high)
Signal is ’1’ if index position is reached,
otherwise ’0’.
Asynch. Parallel Load Input (active low) /
Reset (active low)
Signal is ’0’ if index position is reached,
otherwise ’1’.
Table 14: Operating mode for counter devices compat-
ible with 74HC191 or 74HC193.