IC-MQF Datasheet, PDF (16/37 Pages) IC-Haus GmbH – PROGRAMMABLE 12-BIT Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MQF PROGRAMMABLE 12-BIT ^preliminary
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
I²C Slave Mode (ENSL = 1)
In this mode iC-MQF behaves like an I²C slave with the
device ID 0x55 and the configuration interface permits
write and read accesses to iC-MQF’s internal registers.
For chip release verification purposes an identification
value is stored under ROM address 0x2F; a write ac-
cess to this address is not permitted.
CHPREL
Code
0x22
0x23
Adr 0x2F, bit 7:0 (ROM)
Chip Release
iC-MQ F2
iC-MQ F3
Table 7: Chip Release
END
Code
0
1
Adr 0x02, bit 7
Function
Sin/D converter and line driver disabled
(RAM configuration data invalid)
Restart of Sin/D conversion, line driver active
(RAM configuration data valid)
Table 8: Configuration Enable
For programming iC-MQF via I²C addresses 0x00 to
0x2E need to be written. In doing so, bit 7 of address
0x02 must be set zero initially (END = 0), until all reg-
isters have been configured. Finally, a restart requires
END = 1 to be written without changing other bits of
address 0x02.
Addr 0x02
bit 7 = 0
END = 0
Write registers
0x00 ... 0x2E
Configuration
Addr 0x02
bit 7 = 1
END = 1
Figure 3: Programming via I²C. END is altered by
changing only bit 7 of address 0x02 and
leaving bits 6:0 unchanged.
Rev A1, Page 16/37
Register
RAM Addr
0x00-0x21
0x22-0x2A
0x2B-0x2E
0x2F
0x30-0x33
0x34-0x3A
0x3B-0x3E
0x3F
0x40-0x43
0x44-0x7F
Notes
Read access via I²C slave mode (ENSL = 1)
Content
Configuration data
(see EEPROM addresses 0x00-0x21)
Not available
Configuration data
(see EEPROM addresses 0x2B-0x2E)
Chip release CHPREL(7:0)
Configuration data
(see EEPROM addresses 0x30-0x33)
Not available
Configuration data
(see EEPROM addresses 0x2B-0x2E)
Chip release CHPREL(7:0)
Current error memory* (only active when enabled
by EMASKE; messages will be transferred to
EEPROM Addresses 0x30-0x33)
Not available
*) Upon changing enable register EMASKE, a
double restart of Sin/D conversion (2x END: 0→1)
is essential for the correction of RAM contents.
Table 9: RAM Read Access
Register
RAM Addr
0x00
0x01
0x02
0x03-0x16
0x17
0x18
0x19-0x21
0x2B-0x2E
0x2F-0x3F
0x40-0x43
0x44-0x7F
Write access via I²C slave mode (ENSL = 1)
Access and conditions
Changes possible, no restrictions
Changes possible
(wrong entries for CFGIBN can limit functions)
Changes to bits 6:0 are permitted only when Sin/D
conversion is halted (END = 0, ie. bit 7);
Restarting Sin/D conversion by changing END (bit
7) is permitted only with no changes of operating
mode (bits 6:0 remain as set)
Changes possible, no restrictions
Changes to bits 7:4 and 2:0 are permitted
(ENSL, bit 3 must be kept 1)
Changes possible, no restrictions
Changes possible when Sin/D conversion is halted
(END = 0)
Changes possible, no restrictions
No write access permitted
No write access permitted
Not available
Table 10: RAM Write Access
Notice: The converter function should be halted by
END = 0 for the deletion of errors saved in the EEP-
ROM (Dev-ID 0x50, Addresses 0x30-0x33). Other-
wise active errors could be transferred to the EEP-
ROM again (from addresses 0x40-0x43 if enabled by
EMASKE).