IC-TW11 Datasheet, PDF (16/25 Pages) IC-Haus GmbH – 10-BIT ULTRA LOW POWER MAGNETIC ABSOLUTE ROTARY ENCODER

iC-TW11 10-BIT ULTRA LOW POWER^preliminary
MAGNETIC ABSOLUTE ROTARY ENCODER
CONFIG.spol
Addr. 0x20; bit 6
0
Sample on falling edge (default)
1
Sample on rising edge
Table 15: Sample input polarity
Rev B1, Page 16/25
CONFIG.lpwr
Addr. 0x21; bit 0
0
Normal power operating mode (default)
1
Enable low power mode
Table 19: Low power mode
The sampling mode bit, smod (bit 5) is used to disable
sampling on the rising edge of xSS at the end of an SPI
command packet.
See USING LOW POWER MODE on Page 21 for
more information on using CONFIG.lpwr and low power
mode.
CONFIG.smod Addr. 0x21; bit 5
0
SPI sampling enabled (default)
1
Disable SPI sampling
Table 16: Sampling mode
CONFIG.smod should be set when using the SAMPLE
pin instead of SPI sampling. See USING THE SAMPLE
INPUT on Page 20 for more information.
STATUS Register
The STATUS register is an 8-bit read-only register that
shows the status of the most recent sample.
When reading the STATUS register, it is recommended
to suppress the next sample by setting sup = 1 in the
command packet. This ensures that the status read is
consistent with the previous (most recent) sample. The
STATUS register value is returned in the lower byte of
the response packet.
The IRQ mode bit, imod (bit 3) determines the logic
used to activate IRQ_OUT.
CONFIG.imod
Addr. 0x21; bit 3
0
IRQ_OUT =
IRQ_IN AND conversion complete (default)
1
IRQ_OUT =
IRQ_IN OR conversion complete
STATUS Register
Bit
Name
7:3
-
2
uflo
1
oflo
0
busy
Description
Not used (0)
ADC underflow
ADC overflow
Busy
Addr. 0x22
Table 20: STATUS Register
Table 17: IRQ mode
See USING INTERRUPTS on page 20 for more infor-
mation on using CONFIG.imod.
The ADC underflow bit, uflo (bit 2) indicates that the
Hall signal levels for the most recent sample were too
low. Specifically, STATUS.uflo = 1 if the magnitude of
all three Hall signals was less than 50% of the ADC
full-scale value (256 = 0x100).
The AGC disable bit, noagc (bit 2) is used to disable au-
tomatic control of the Hall sensor gain. The AGC should
only be disabled if an alternate gain control system is
implemented in the host µP.
The ADC overflow bit, oflo (bit 1) indicates that the Hall
signal levels for the most recent sample were too high.
Specifically, STATUS.oflo = 1 if the magnitude of any
Hall signal was more than 99% of the ADC full-scale
value (506 = 0x1FA).
CONFIG.noagc Addr. 0x21; bit 2
0
Automatic gain control active (default)
1
Disable automatic gain control
Table 18: AGC disable
The busy bit, busy (bit 0) indicates whether or not a
conversion is in process. If STATUS.busy = 0, the con-
version is complete and STATUS.uflo and STATUS.oflo
are valid. If STATUS.busy = 1, the conversion is in pro-
cess and STATUS.uflo and STATUS.oflo are undefined.
If CONFIG.noagc = 1, proper Hall array gain must be
set by writing the appropriate value to the GAIN Regis-
ter (0x23).
The low power mode bit, lpwr (bit 0) is used to reduce
the power consumption of the chip by disabling the Hall
sensor filters and shortening the conversion time.
GAIN Register
The GAIN register is an 8-bit read/write register that
determines the Hall array gain.
When reading the GAIN register, it is recommended
to suppress the next sample by setting sup = 1 in the
command packet. This ensures that the gain value read
is the actual gain that was used with the previous (most