IC-DC_17 Datasheet, PDF (16/19 Pages) IC-Haus GmbH – 2-CHANNEL BUCK/BOOST DC/DC CONVERTER

iC-DC
2-CHANNEL BUCK/BOOST DC/DC CONVERTER
DESCRIPTION OF THE APPLICATION
Rev B1, Page 16/19
Selecting the coil
The coil should be designed for a DC current and sat-
uration current of min. 0.8 A. A small internal resistor
in the coil reduces loss and increases converter effi-
ciency. At a low supply voltage this internal resistor can
determine the maximum available output current.
The EMI caused by the coil should be taken into consid-
eration. Toroidal core coils have little noise radiation yet
are expensive and difficult to install. Bar core coils are
reasonably priced and easier to use yet have a higher
noise emittance. For modest EMI requirements inex-
pensive radio interference suppression coils of several
tens of µH are suitable^∗.
Printed circuit board layout
The GND path from the switching converter and from
each linear regulator should be strictly separated to
avoid cross couplings. The neutral point of all GND
paths is the GND connection at iC-DC. It is possible
and not critical, however, to route GND from supply VB
and the base point of capacitors C_VH, C_VH1 and C_VH2
together to the neutral point. The capacitors should be
very close to their relevant pins, however.
Blocking capacitors for supply VB should be arranged
as close as possible to pins VB and GND. The capac-
itors for outputs VCC1 and VCC2 should be placed
directly at the load and not at the IC to also block inter-
ferences which are coupled via the wiring to the load.
Selecting the capacitors
For selecting back-up capacitors C_VH, C_VH1 and C_VH2
please ref to elec. char. item 307, 311, 315. As the
residual ripple of intermediate voltages VH1 and VH2
does not affect output voltages VCC1 and VCC2 thanks
to the back-end linear regulators, a small capacitor is
sufficient without any specific demands being made
of the internal resistor. A combination of electrolytic
and ceramic capacitors (e.g. 3.3 µF || 100 nF) is recom-
mended. Before using tantalum capacitors, the user
must verify whether these are suitable for the residual
AC amplitude (residual ripple) at pins VH1 and VH2.
The ground planes underneath the wiring of output volt-
ages VCC1, VCC2, POE1, and POE2 should be kept
separate from the ground planes of switching convert-
ers VH, VH1, and VH2. The ground planes must be
connected up at a neutral point (see Figure 8).
The thermal pad should be connected to the PCB by
an appropriate ground plane. The resulting power dissi-
pation can be transferred to a different wiring layer, e.g.
a ground plane, by vias directly underneath the IC.
Stability of the linear regulators across the entire load
area is guaranteed if the values given in the electrical
characteristics are selected for CVCC1 and CVCC2.
The suppression of interference voltage is improved by
using small capacitor series resistors. A combination of
tantalum and ceramic capacitors is also recommended
in this case. If one of the two outputs remains open,
this capacitor can be omitted.
To avoid feedback of interference from supply voltage
VB onto output voltages VCC1 and VCC2, blocking
should be provided directly at pin VB. A combination of
tantalum and ceramic capacitors (e.g. 1 µF || 100 nF) is
also recommended in this case.
Figure 8: Example layout: evaluation board DC1D
∗ _{e.g.: Würth no.: 74437324220 (22µH, 1A, SMD shielded), Siemens Matsushita B78108-S1223-J (22 µH/1 A, axial), TDK series}
NLC565050T-. . . (SMD), TOKO series 10RF459-. . . (SMD shielded)