IC-MA Datasheet, PDF (14/18 Pages) IC-Haus GmbH – ANGULAR HALL SENSOR / ENCODER

iC-MA
ANGULAR HALL SENSOR / ENCODER
Rev B3, Page 14/18
In the various chain modes multiple iC-MAs can be ar-
ranged in a chain (see Figure 11) where all of the de-
vices are connected by a shared CLK line (pin B). The
NEN input is evaluated synchronously with the rising
CLK edge. If the NEN input is switched to low, the
device is active during the following CLK cycle(s). To
allow the devices to be cascaded a delayed enable sig-
nal is generated at output pin NENO (pin D) with which
the follow-on device can be activated. If the NEN in-
put of the first device in the chain is reset to high, all
devices in the chain are deactivated. Bus lines A (pin
A) and C (pin C) are activated by tristate output stages
which are high impedance when NEN is high and CLK
is low and also following the second rising CLK edge.
second clock pulse deactivates the current device and
activates the following device in the chain with a low
signal at its NEN input.
S chain mode
In S chain mode the non-inverted sine (port A) and co-
sine (port C) signals are presented to the bus during
the first clock pulse, with the mean of the two signals
(VREF, port A) and the amplification signal GAIN (port
C) following on the positive CLK edge of the next pulse.
Each device is thus active for two clock pulses. The
falling CLK edge in the second clock pulse deactivates
the current device and activates the following device in
the chain with a low signal at its NEN input.
AB chain mode
In AB chain mode two A/B digital incremental signals
are generated at ports A and C. The two square-wave
signals are phase shifted at either +90° or -90°, de-
pending on the direction of rotation. Following a CLK
pulse the next device in the chain is enabled. Here the
falling CLK edge deactivates the current device (e.g.
MA 1 in Figure 11) and activates the next device in the
chain (MA 2) with a low signal at its NEN input. After
a device has been activated the two bus lines A (port
A) and B (port C) are first switched to low (see Figure
12). This is then followed by the incremental signals
being output, starting at the zero position. In the event
of error the bus lines remain low.
D chain mode
In D chain mode differential sine and cosine signals
are generated at ports A and C. During the first clock
pulse signals PSIN and PCOS are presented to the
bus; during the second pulse signals NSIN and NCOS
are on the bus (see Figure 12). In this mode each
device is thus active for two clock pulses. During the
first clock pulse the non-inverted sine (port A) and co-
sine (port C) signals are first presented to the bus, with
the inverted signals following on the positive CLK edge
during the second pulse. The falling CLK edge in the
The sine and cosine signals can be assessed using
signal VREF. Signal GAIN (pin D) indicates iC-MA’s in-
ternal amplification (see Electrical Characteristics No.
207) and can be used to estimate the signal amplitude
of the internal Hall sensor. The GAIN signal can also
be used to adjust the rotary axis of the magnet to the
center of the chip.
NEN
CLK
NENO
5
4
3
2
1
0
0
A
C
100 200 300 400 500 600 700
Time [µs]
Figure 13: Bus signals and control signals in S
chain mode