IC-LNG_14 Datasheet, PDF (14/30 Pages) IC-Haus GmbH – 16-BIT OPTO ENCODER

iC-LNG 16-BIT OPTO ENCODER ^preliminary
WITH SPI AND SERIAL / PARALLEL OUTPUTS
Rev B1, Page 14/30
OPERATING REQUIREMENTS: Shift Register
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40°C to 125°C, unless otherwise specified.
Item Symbol Parameter
No.
Conditions
Min.
Unit
Max.
I101 T_CLK
I102 t_NC
Permissible Clock Period
Setup Time:
NSL lo before CLK lo → hi
1/fin(CLK)
30
ns
I103 t_NO
Propagation Delay:
DOUT stable after NSL hi → lo
(Elec. Char. No. A02)
I104 t_CO
Propagation Delay:
DOUT stable after Clock Edge CLK
(Elec. Char. No. A03)
I105 t_IC
Setup Time:
DIN stable before CLK lo → hi
30
ns
I106 t_CI
Hold Time:
DIN stable after CLK lo → hi
30
ns
I107 t_NN
Wait Time:
between NSL lo → hi and NSL hi → lo
60
ns
NSL
CLK
DOUT
DIN
t_NC
t_NO
t_CO
t_IC t_CI
T_CLK
Figure 3: Shift register timing
t_NN
t_NO