HYMD116645D8J-D43 Datasheet, PDF (9/18 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD116645D(L)8J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400 (D43)
Min
Max
DDR400 (D4)
Unit
Min
Max
Row Cycle Time
tRC
55
-
58
-
ns
Auto Refresh Row Cycle Time
tRFC
70
-
70
-
ns
Row Active Time
Active to Read with Auto Precharge Delay
tRAS
40
70K
40
70K
ns
tRAP
tRCD
-
tRCD
-
ns
Row Address to Column Address Delay
tRCD
15
-
18
-
ns
Row Active to Row Active Delay
tRRD
10
-
10
-
ns
Column Address to Column Address Delay
tCCD
1
-
1
-
CK
Row Precharge Time
tRP
15
-
18
-
ns
Write Recovery Time
tWR
15
-
15
-
ns
Write to Read Command Delay
tWTR
2
-
2
-
CK
(tWR/tCK)
(tWR/tCK)
Auto Precharge Write Recovery + Precharge Time tDAL
+
-
+
-
CK
(tRP/tCK)
(tRP/tCK)
System Clock Cycle Time
CL = 3
tCK
5
10
5
10
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Clock edge Skew
tDQSCK -0.55
0.55
-0.55
0.55
ns
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
tDQSQ
-
0.4
-
0.4
ns
tHP
tQH
-tQHS
-
tHP
-tQHS
-
ns
min
tHP
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
Data Hold Skew Factor
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
tQHS
tHZ
tLZ
tIS
tIH
tIS
tIH
-
0.5
-
0.5
ns
tAC(Max)
tAC(Max) ns
tAC(min) tAC(Max) tAC(min) tAC(Max) ns
0.6
-
0.6
-
ns
0.6
-
0.6
-
ns
0.6
-
0.6
-
ns
0.6
-
0.6
-
ns
Note
16
15
1, 10
1,9
10
17
17
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
Rev. 0.0 / Apr. 2003
9