HYMD116645D8J-D43 Datasheet, PDF (8/18 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD116645D(L)8J
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
D43 D4 -J
One bank; Active Precharge; tRC=tRC(min);
Operating Current
tCK=tCK(min); DQ,DM and DQS inputs changing
IDD0 _{twice per clock cycle; address and control inputs}
960
720
changing once per clock cycle
One bank; Active - Read Precharge; Burst Length
Operating Current
IDD1 =2; tRC=tRC(min); tCK=tCK(min); address and
960
880
control inputs changing once per clock cycle
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
160
160
/CS=High, All banks idle ; tCK=tCK(min); CKE=
Idle Standby Current
IDD2F High; address and control inputs changing once
480
320
per clock cycle. VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
160
160
Active Standby
Current
/CS=HIGH; CKE=HIGH; One bank; Active
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
IDD3N DM and DQS inputs changing twice per clock
520
320
cycle; Address and other control inputs changing
once per clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
1840
1840
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM, and DQS
inputs changing twice per clock cycle
1840
1840
Auto Refresh Current
IDD5
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz,
12*tCK for DDR333 at 166Mhz; distributed refresh
1440
1280
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
Low Power
16
8
16
8
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to the
IDD7 _{following page for detailed test condition}
2400
2400
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.0 / Apr. 2003
8