HYMD564G726CFP8N-D43 Datasheet, PDF (8/23 Pages) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs

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184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64Mb x 72 ECC Registered DIMM: HYMD564G726CFP8N
Symbol
Test Condition
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Speed
DDR400B
DDR333
1820
1730
2180
2000
540
965
855
1190
2540
2360
2720
2540
2990
2810
495
477
3890
3800
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.4 / Aug. 2006
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