HYMD264G726B4-M Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD264G726B(L)4-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK= tCK(min) ; DQ,DM and DQS inputs
changing twice per clock cycle ; address and
2810 2630 2630 2450 mA
control inputs changing once per clock cycle
Operating Current
IDD1
One bank ; Active - Read - Precharge ; Burst
Length = 2 ; tRC=tRC(min); tCK= tCK(min) ;
address and control inputs changing once per ^{2810 2630 2630 2450 mA}
clock cycle
Precharge Power Down
Standby Current
IDD2P
All banks idle ; Power down mode ; CKE= Low,
tCK= tCK(min)
830
mA
Idle Standby Current
IDD2F
/CS = High, All banks idle ; tCK= tCK(min) ;
CKE = High ; address and control inputs
changing once per clock cycle. VIN = VREF for
1550
1460
1460
1370
mA
DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active ; Power down mode ; CKE=
Low, tCK= tCK(min)
920
mA
Active Standby Current
IDD3N
/CS= HIGH; CKE = HIGH; One bank; Active-
Precharge; tRC = tRAS(max); tCK = t CK
(max); DQ, DM and DQS inputs changing twice 1730 1640 1640 1550 mA
per clock cycle; Address and other control
inputs changing once per clock cycle
Operating Current
IDD4R
Burst = 2 ; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK= tCK (min); IOUT =
0mA
3710
3350
3350
3170
Operating Current
Burst = 2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing
once per clock cycle; tCK = tCK (min); DQ, DM, ^{3890 3710 3710 3530}
mA
and DQS inputs changing twice per clock cycle
Auto Refresh Current
IDD5
tRC = tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B at
133Mhz; distributed refresh
3590
3410 3410 3230
Self Refresh Current
IDD6
CKE =< 0.2V; External clock on; ^Normal
tCK = tCK(min)
Low Power
404
377
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
5510 5330 5330 5150 mA
Rev. 0.1/Oct. 02
8