HYMD232G726L8-K Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD232G726(L)8-K/H/L
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
-K -H -L
Unit Note
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
1505 1505 1460 mA
Operating Current
One bank; Active - Read - Precharge; Burst Length
IDD1 =2; tRC=tRC(min); tCK=tCK(min); address and
1730 1730 1640 mA
control inputs changing once per clock cycle
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
830 830 785 mA
/CS=High, All banks idle; tCK=tCK(min); CKE=High
Idle Standby Current
IDD2F ; address and control inputs changing once per
1010
mA
clock cycle. VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
875 875 830 mA
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
Active Standby Current IDD3N DM and DQS inputs changing twice per clock cycle;
1100
mA
Address and other control inputs changing once per
clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
2495 2495 2090
Operating Current
Burst=2; Writes; Continuous burst; One bank active;
IDD4W
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM, and DQS inputs
2720
2720
2360
mA
changing twice per clock cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
2240 2240 2105
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
377
363.5
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
3395 3395 3170 mA
Rev. 0.6/Oct. 02
8