HYMD232G726L8-K Datasheet, PDF (1/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

DESCRIPTION
32Mx72 bits
Registered DDR SDRAM DIMM
HYMD232G726(L)8-K/H/L
Hynix HYMD232G726(L)8-K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Mem-
ory Modules(DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232G726(L)8-K/H/L
series consists of nine 32Mx8 DDR SDRAM in 400mil TSOPII packages on a 184pin glass-epoxy substrate. Hynix
HYMD232G726(L)8-K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry
stanard. It is suitable for easy interchange and addition.
Hynix HYMD232G726(L)8-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper-
ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232G726(L)8-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 256MB (32M x 72) Registered DDR DIMM based on • Fully differential clock operations (CK & /CK) with
32Mx8 DDR SDRAM
100MHz/125MHz/133MHz
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Error Check Correction (ECC) Capability
• Programmable CAS Latency 2 / 2.5 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Registered inputs with one-clock delay
• tRAS Lock-out function supported
• Phase-lock loop (PLL) clock driver to reduce loading • Internal four bank operations with single pulsed RAS
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• Auto refresh and self refresh supported
• All inputs and outputs are compatible with SSTL_2
interface
• 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD232G726(L)8-K
HYMD232G726(L)8-H
HYMD232G726(L)8-L
Power Supply
VDD=2.5V
VDDQ=2.5V
Clock Frequency
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
Interface
Form Factor
SSTL_2
184pin Registered DIMM
5.25 x 1.7 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6/Oct. 02
1