HYMD232G726L8-K Datasheet, PDF (15/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0
Number of Bytes written into serial memory at module
manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=2.0(tCK)
24 DDR SDRAM access time from clock at CL=2.0(tAC)
25 DDR SDRAM cycle time at CL=1.5(tCK)
26 DDR SDRAM access time from clock at CL=1.5(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh time ( tRC)
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
43 Maximum cycle time (tCK max)
44 Maximim DQS-DQ skew time(tDQSQ)
45 Maximum read data hold skew factor(tQHS)
46~61 Superset information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
HYMD232G726(L)8-K/H/L
Bin Sort : K(DDR266A@CL=2), H(DDR266B@CL=2.5), L(DDR200@CL=2)
Function Supported
K
H
L
128 Bytes
256 Bytes
DDR SDRAM
13
10
1Bank
72 Bits
-
SSTL 2.5V
7.5ns
7.5ns
8ns
+/-0.75ns +/-0.75ns +/-0.8ns
ECC
7.8us & Self refresh
x8
x8
1 CLK
2,4,8
4 Banks
2, 2.5
0
1
Registered, PLL
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
7.5ns
10ns
10ns
+/-0.75ns +/-0.75ns +/-0.8ns
-
-
20ns
20ns
20ns
15ns
15ns
15ns
20ns
20ns
20ns
45ns
45ns
50ns
256MB
0.9ns
0.9ns
1.1ns
0.9ns
0.9ns
1.1ns
0.5ns
0.5ns
0.6ns
0.5ns
0.5ns
0.6ns
Undefined
65ns
65ns
70ns
75ns
75ns
80ns
12ns
12ns
12ns
0.5ns
0.5ns
0.6ns
0.75ns 0.75ns 0.75ns
Undefined
Initial release
-
Hexa Value
K
H
L
80h
08h
07h
0Dh
0Ah
01h
48h
00h
04h
75h
75h
80h
75h
75h
80h
02h
82h
08h
08h
01h
0Eh
04h
0Ch
01h
02h
26h
C0h
75h
A0h
A0h
75h
75h
80h
00h
00h
50h
50h
50h
3Ch
3Ch
3Ch
50h
50h
50h
2Dh
2Dh
32h
40h
90h
90h
B0h
90h
90h
B0h
50h
50h
60h
50h
50h
60h
00h
41h
41h
46h
4Bh
4Bh
50h
30h
30h
30h
32h
32h
3Ch
75h
75h
75h
00h
00h
CFh
FAh
94h
Note
1
1
2
2
2
2
2
2
Rev. 0.6/Oct. 02
15