HYMD216M646DL6-D43 Datasheet, PDF (8/23 Pages) Hynix Semiconductor – 200pin Unbuffered DDR SDRAM SO-DIMMs based on 256Mb D ver. (TSOP)

11
200pin Unbuffered DDR SDRAM SO-DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
128MB, 32M x 64 Unbuffered SO-DIMM: HYMD216M646D[L][P]6
Symbol
Test Condition
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
CKE=<0.2V; External clock on; tCK ^Normal
=tCK(min)
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
-D43
360
400
40
240
60
160
800
800
600
12
6
1000
Speed
-J
-K
320
280
400
360
40
40
200
160
60
60
140
120
760
680
760
680
560
520
12
12
6
6
960
880
Unit Note
-H
280
mA
360
mA
40
mA
160
mA
60
mA
120
mA
680
mA
680
mA
520
mA
12
mA
6
mA
880
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
8