HYMD216M646DL6-D43 Datasheet, PDF (10/23 Pages) Hynix Semiconductor – 200pin Unbuffered DDR SDRAM SO-DIMMs based on 256Mb D ver. (TSOP)

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200pin Unbuffered DDR SDRAM SO-DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]6
Symbol
Test Condition
Speed
DDR400B DDR333 DDR266A DDR266B
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
600
520
440
440
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
IDD1 Length=2; tRC=tRC(min); tCK=tCK(min); address
640
600
520
520
and control inputs changing once per clock cycle
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
80
80
80
80
/CS=High, All banks idle; tCK=tCK(min); CKE=
IDD2F High; address and control inputs changing once
480
400
320
320
per clock cycle. VIN=VREF for DQ, DQS and DM
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
120
120
120
120
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
IDD3N and DQS inputs changing twice per clock cycle;
440
380
320
320
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
IDD4R active; Address and control inputs changing once
1040
960
840
840
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
1040
960
840
840
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
IDD5 10*tCK for DDR266A & DDR266B at 133Mhz; dis-
840
800
720
720
tributed refresh
CKE=<0.2V; External clock on; tCK Normal
24
24
24
24
IDD6 _=tCK(min)
Low Power
12
12
12
12
IDD7
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
1240
1160
1040
1040
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev.
1.1
/
May.
2005
10