HY62U8200B Datasheet, PDF (8/12 Pages) Hynix Semiconductor – 256K x8 bit 3.0V Low Power CMOS slow SRAM

Y62U8200B Series
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /WE, a low /CS1 and a high CS2. A write begins at the latest
transition among /CS1 going now, CS2 going high and /WE going low: A write ends at the earliest
transition among /CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of
write to the end of write.
.
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 is applied in case a write ends as
/CS1, or /WE going high, and tWR2 is applied in case a write ends at CS2 going low.
5. If /OE, CS2 and /WE are in the read mode during this period, and the I/O pins are in the output low-Z
state, input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state.
7. Dout is the read data of the new address.
8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite
phase leading to the outputs should not be applied.
Rev 06 / Apr. 2001
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