HY62SF16804B Datasheet, PDF (8/10 Pages) Hynix Semiconductor – 512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM

HY62SF16804B
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and low /UB and /or /LB
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0°C to 70°C / -40°C to 85°C
Symbol
Parameter
VDR
Vcc for Data Retention
ICCDR Data Retention Current
tCDR
tR
Chip Deselect to Data
Retention Time
Operating Recovery Time
Test Condition
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VIN < Vss+0.2V
Vcc=1.5V, /CS > Vcc - 0.2V or LL
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VIN < Vss+0.2V
SL
See Data Retention Timing Diagram
Min Typ Max Unit
1.2
-
2.3
V
-
1
-
-
0
-
tRC(2)
-
12 uA
8
uA
-
ns
-
ns
Notes:
1. Typical values are under the condition of TA = 25°C .
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC
1.65V
VIH
VDR
/CS or
/UB & /LB
Vss
DATA RETENTION MODE
tCDR
tR
/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V
Rev.00/May. 2001
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