HY62SF16804B Datasheet, PDF (6/10 Pages) Hynix Semiconductor – 512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM

TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
ADDR
/CS
/UB ,/ LB
/OE
Data
Out
High-Z
tRC
tAA
tACS
tBA
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
HY62SF16804B
tOH
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
Data
Out
tAA
tOH
Previous Data
tOH
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS and low /UB and /or /LB
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.00/May. 2001
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