HY5V26CF Datasheet, PDF (8/14 Pages) Hynix Semiconductor – 4 Banks x 2M x 16bits Synchronous DRAM

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
HY5V26C(L/S)F
Parameter
System Clock Cycle ^{CAS Latency = 3}
Time
CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Access Time From ^{CAS Latency = 3}
Clock
CAS Latency = 2
Data-Out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output ^{CAS Latency = 3}
in High-Z Time
CAS Latency = 2
Symbol
-6
Min Max
tCK3
tCK2
6
1000
10
tCHW
2.5
-
tCLW
2.5
-
tAC3
-
5.4
tAC2
-
6
tOH
2.7
-
tDS
1.5
-
tDH
0.8
-
tAS
1.5
-
tAH
0.8
-
tCKS
1.5
-
tCKH
0.8
-
tCS
1.5
-
tCH
0.8
-
tOLZ
1
-
tOHZ3
2.7 5.4
tOHZ2
2.7 5.4
-K
Min Max
7.5
1000
7.5
2.5
-
2.5
-
-
5.4
-
5.4
2.7
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1
-
2.7 5.4
2.7 5.4
-H
Min Max
7.5
1000
10
2.5
-
2.5
-
-
5.4
-
6
2.7
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1
-
2.7 5.4
3
6
-8
Min Max
8
1000
10
3
-
3
-
-
6
-
6
3
-
2
-
1
-
2
-
1
-
2
-
1
-
2
-
1
-
1
-
3
6
3
6
-P
Min Max
10
1000
10
3
-
3
-
-
6
-
6
3
-
2
-
1
-
2
-
1
-
2
-
1
-
2
-
1
-
1
-
3
6
3
6
-S
Min Max
Unit
Note
10
ns
1000
12
ns
3
-
ns
1
3
-
ns
1
-
6
ns
2
-
6
ns
3
-
ns
2
-
ns
1
1
-
ns
1
2
-
ns
1
1
-
ns
1
2
-
ns
1
1
-
ns
1
2
-
ns
1
1
-
ns
1
1
-
ns
3
6
ns
3
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.9/Jul. 02
8