HY5V66GF Datasheet, PDF (7/11 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
-H
-P
Symbol
Unit
Min
Max
Min
Max
System clock
cycle time
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
7.5
10
ns
1000
1000
10
10
ns
Clock high pulse width
tCHW
2.5
-
3
-
ns
Clock low pulse width
tCLW
2.5
-
3
-
ns
Access time from
clock
CAS Latency = 3
CAS Latency = 2
tAC3
tAC2
5.4
6
ns
6
-
6
ns
Data-out hold time
tOH
2.7
-
3
-
ns
Data-Input setup time
tDS
1.5
-
2
-
ns
Data-Input hold time
tDH
0.8
-
1
-
ns
Address setup time
tAS
1.5
-
2
-
ns
Address hold time
tAH
0.8
-
1
-
ns
CKE setup time
tCKS
1.5
-
2
-
ns
CKE hold time
tCKH
0.8
-
1
-
ns
Command setup time
tCS
1.5
-
2
-
ns
Command hold time
tCH
0.8
-
1
-
ns
CLK to data output in low Z-time
tOLZ
1.5
-
1
-
ns
CLK to data output ^{CAS Latency = 3}
in high Z-time
CAS Latency = 2
tOHZ3
tOHZ2
ns
5.4
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Note
1
1
2
1
1
1
1
1
1
1
1
HY5V66GF
Rev. 0.4/Nov. 01
7