HY5V66GF Datasheet, PDF (1/11 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

HY5V66GF
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hyundai HY5V66GF is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY5V66GF is organized as 4banks of 1,048,576x16.
HY5V66GF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output volt-
age levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply ^Note)
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface ^{• 4096 refresh cycles / 64ms}
• JEDEC standard 60Ball FD-BGA with 0.65mm of
pin pitch
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
• All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4 or 8 for Interleave Burst
• Data mask function by UDQM or LDQM
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY5V66GF-H
HY5V66GF-P
Clock Frequency
133MHz
100MHz
Power
Normal
Organization
4Banks x 1Mbits
x16
Interface
LVTTL
Package
10.1x 6.4 60Ball 0.65
Pin -pitch FD-BGA
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.4/Nov. 01
1