HY5DU561622FLFP Datasheet, PDF (7/27 Pages) Hynix Semiconductor – 256Mb DDR SDRAM

HY5DU561622F(L)FP
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1 CKEn
/CS
/RAS /CAS /WE ADDR A10/AP BA
Extended Mode Register Set^1,2
H
X
L
L
L
L
OP code
Mode Register Set^1,2
H
X
L
L
L
L
OP code
Device Deselect¹
H
X
X
X
H
X
X
No Operation¹
L
H
H
H
Bank Active¹
H
X
L
L
H
H
RA
V
Read¹
L
H
X
L
H
L
H
CA
V
Read with Autoprecharge^1,3
H
Write¹
L
H
X
L
H
L
L
CA
V
Write with Autoprecharge^1,4
H
Precharge All Banks^1,5
H
X
H
X
L
L
H
L
X
Precharge selected Bank¹
L
V
Read Burst Stop¹
H
X
L
H
H
L
X
Auto Refresh¹
H
H
L
L
L
H
X
Entry
H
L
L
L
L
H
Self Refresh¹
Exit
L
H
H
X
X
X
X
L
H
H
H
H
X
X
X
Entry
H
L
Precharge Power
L
H
H
H
X
Down Mode¹
Exit
L
H
H
X
X
X
L
H
H
H
H
X
X
X
Active Power
Entry
H
L
Down Mode¹
L
V
V
V
X
Exit
L
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note:
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting EVSJOH Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Precharge command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been
completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
*For more information about Truth Table, refer to “Device Operation” section in Hynix website.
Rev. 1.0 /Nov. 2007
7