HY57V56820B Datasheet, PDF (7/12 Pages) Hynix Semiconductor – 4 Banks x 8M x 8Bit Synchronous DRAM

HY57V56820B(L)T
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
-6
Symbol
Min Max
-K
Min Max
-H
Min Max
-8
Min Max
-P
Min Max
-S
Min Max
Unit Note
System Clock
Cycle Time
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
6
7.5
7.5
8
10
10
ns
1000
1000
1000
1000
1000
1000
10
7.5
10
10
10
12
ns
Clock High Pulse Width
tCHW
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Access Time
From Clock
CAS Latency = 3 tAC3
CAS Latency = 2 tAC2
-
5.4
-
5.4
-
5.4
-
6
-
6
-
6
ns
2
-
6
-
5.4
-
6
-
6
-
6
-
6
ns
Data-Out Hold Time
tOH
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z Time tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
ns
CLK to Data
CAS Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 3
6
3
6
3
6
ns
Output in High-Z
Time
CAS Latency = 2 tOHZ2 2.7 5.4 2.7 5.4 3
6
3
6
3
6
3
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 1.4/Mar. 02
7