HY57V56820B Datasheet, PDF (6/12 Pages) Hynix Semiconductor – 4 Banks x 8M x 8Bit Synchronous DRAM

HY57V56820B(L)T
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-6 -K -H -8 -P -S
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
130 120 120 120 110 110 mA 1
Precharge Standby Current ^{IDD2P CKE ≤ VIL(max), tCK = 15ns}
in Power Down Mode
IDD2PS CKE ≤ VIL(max), tCK = ∞
2
mA
1
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
IDD2N Input signals are changed one time during
30
Precharge Standby Current
in Non Power Down Mode
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
mA
IDD2NS ^{CKE ≥ VIH(min), tCK = ∞}
15
Input signals are stable.
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = 15ns
IDD3PS CKE ≤ VIL(max), tCK = ∞
5
mA
5
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
IDD3N Input signals are changed one time during
40
Active Standby Current
in Non Power Down Mode
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
mA
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
30
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
CL=3
CL=2
150 130 130 130 110 110
mA 1
140 140 140 140 120 120
Auto Refresh Current
IDD5 tRRC ≥ tRRC(min), All banks active
240 220 220 200 200 200 mA 2
Self Refresh Current
IDD6 CKE ≤ 0.2V
3
mA 3
1.5
mA 4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V56820BT-6/H/8/P/S
4.HY57V56820BLT-6/H/8/P/S
Rev. 1.4/Mar. 02
6