HYMD512M646BF8-D43 Datasheet, PDF (6/17 Pages) Hynix Semiconductor – 200pin Unbuffered DDR SDRAM SO-DIMMs based on 512Mb B ver. (FBGA)

200pin Unbuffered DDR SDRAM
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
1GB, 128M x 64 Unbuffered SO-DIMM: HYMD512M646B[L]F[P]8
Symbol
Test Condition
Speed
DDR400B DDR333 DDR266B
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
CKE=<0.2V; External clock on;
tCK =tCK(min)
Normal
Low Power
1480
1880
160
560
192
680
2520
2520
2680
80
40
1400
1720
160
560
192
640
2280
2280
2520
80
40
1240
1480
160
560
192
600
1960
1960
2360
80
40
IDD7
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
4600
3960
3320
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
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