HY57V653220BTC Datasheet, PDF (6/12 Pages) Hynix Semiconductor – 4 Banks x 512K x 32Bit Synchronous DRAM

HY57V653220B
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Parameter
Operating Current
Precharge Standby
Current
in power down mode
Precharge Standby
Current
in non power down mode
Active Standby Current
in power down mode
Active Standby Current
in non power down mode
Burst Mode Operating
Current
Auto Refresh Current
Self Refresh Current
Symbol
Test Condition
-5
-55
Speed
-6
-7
-8
-10P
-10
Unit
Not
e
IDD1
Burst Length=1, One bank active
tRAS ≥ tRAS(min), tRP ≥ tRP(min),
IOL=0mA
200 190 180 170 150 150 150 mA
1
IDD2P
CKE ≤ VIL(max), tCK = 15ns
IDD2PS CKE ≤ VIL(max), tCK = ∞
2
mA
2
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =
IDD2N
15ns
Input signals are changed one time during
15
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
mA
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
IDD3P
CKE ≤ VIL(max), tCK = 15ns
IDD3PS CKE ≤ VIL(max), tCK = ∞
3
mA
3
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =
IDD3N
15ns
Input signals are changed one time during
40
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
mA
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable
25
IDD4
tCK ≥ tCK(min),
CL=3
280 260 240 210 180 180 160
tRAS ≥ tRAS(min), IOL=0mA
mA
1
All banks active
CL=2
160 160 160 160 160 160 140
IDD5
tRRC ≥ tRRC(min), All banks active
250 235 220 210 190 190 190 mA
2
IDD6
CKE ≤ 0.2V
2
mA
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
Rev.1.6/Dec. 01
6