HY57V653220BTC Datasheet, PDF (2/12 Pages) Hynix Semiconductor – 4 Banks x 512K x 32Bit Synchronous DRAM

PIN CONFIGURATION
VDD
1
DQ0 2
VDDQ
3
DQ1 4
DQ2 5
VSSQ
6
DQ3 7
DQ4 8
VDDQ
9
DQ5 10
DQ6 11
VSSQ
12
DQ7 13
NC 14
VDD
15
DQM0 16
/W E 17
/CAS 18
/RAS 19
/CS 20
NC 21
BA0 22
BA1 23
A10/AP 24
A0 25
A1 26
A2 27
DQM2 28
VDD
29
NC 30
DQ16 31
VSSQ
32
DQ17 33
DQ18 34
VDDQ
35
DQ19 36
DQ20 37
VSSQ
38
DQ21 39
DQ22 40
VDDQ
41
DQ23 42
VDD
43
PIN DESCRIPTION
86pin TSO P II
400m il x 875m il
0.5m m pin pitch
86
VSS
85 DQ15
84
VSSQ
83 DQ14
82 DQ13
81
VDDQ
80 DQ12
79 DQ11
78
VSSQ
77 DQ10
76 DQ9
75
VDDQ
74 DQ8
73
NC
72
VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58
VSS
57 NC
56 DQ31
55
VDDQ
54 DQ30
53 DQ29
52
VSSQ
51 DQ28
50 DQ27
49
VDDQ
48 DQ26
47 DQ25
46
VSSQ
45 DQ24
44
VSS
HY57V653220B
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A10
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev.1.6/Dec. 01
2