HMT451S6MMP8C-S6 Datasheet, PDF (6/40 Pages) Hynix Semiconductor – 204pin DDR3 SDRAM SODIMM

HMT451S6MMP(R)8C
2. Pin Architecture
2.1 Pin Definition
Pin Name
Description
CK[1:0] Clock Inputs, positive line
2
CK[1:0] Clock Inputs, negative line
2
CKE[1:0] Clock Enables
2
RAS
Row Address Strobe
1
CAS
Column Address Strobe
1
WE
Write Enable
1
S[1:0]
A[9:0], A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
ODT[1:0]
SCL
SDA
SA[1:0]
Chip Selects
2
Address Inputs
14
Address Input/Autoprecharge
1
Address Input/Burst Stop
1
SDRAM Bank Address
3
On-die termination control
2
Serial Presence Detect (SPD) Clock
input
1
SPD Data Input/Output
1
SPD address
2
Pin Name
DQ[63:0]
DM[7:0]
DQS[7:0]
DQS[7:0]
RESET
TEST
EVENT
Description
Data Input/Output
64
Data Masks
8
Data strobes
8
Data strobes complement
8
Reset pin
1
Logic Analyzer specific test pin (No
connect on SODIMM)
1
Temperature event pin
1
V_DD
Core and I/O power
18
V_SS
Ground
52
V_REFDQ
Input/Output Reference
2
V_REFCA
V_DDSPD SPD and Temp sensor power
1
Vtt
Termination voltage
2
NC
Reserved for future use
2
Total 204
Rev. 0.2 / Apr. 2009
6