HY5Y7A2DLM-HF Datasheet, PDF (5/26 Pages) Hynix Semiconductor – 4Banks x 4M x 32bits Synchronous DRAM

Preliminary
HY5Y7A2DLM-HF
4Banks x 4M x 32bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 32 I/O Low Power Synchronous DRAM
PASR, TCSR
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
CLK
4Mx32 BANK 3
Row
CKE
Row Active
Pre
4Mx32 BANK 2
4Mx32 BANK 1
CS
Decoder
4Mx32 BANK 0
RAS
CAS
WE
U/LDQM
Refresh
Column Active
Column
Pre
Decoder
Memory
Cell
Array
Column decoders
DQ0
DQ31
Bank Select
Column Add
Counter
A0
Address
A1
Register
Burst
Counter
A12
Mode Register
CAS Latency
Data Out Control
BA1
BA0
Rev. 0.1 / Feb. 2004
5