HY5Y7A2DLM-HF Datasheet, PDF (20/26 Pages) Hynix Semiconductor – 4Banks x 4M x 32bits Synchronous DRAM

Preliminary
HY5Y7A2DLM-HF
4Banks x 4M x 32bits Synchronous DRAM
DC CHARACTERISTICS II (TA= -25 to 70^oC)
Parameter
Symbol
Test Condition
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 15ns
IDD2PS CKE ≤ VIL(max), tCK = ∞
Precharge Standby Current
in Non Power Down Mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = 15ns
IDD3PS CKE ≤ VIL(max), tCK = ∞
Active Standby Current
in Non Power Down Mode
Burst Mode Operating
Current
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5 tRC ≥ tRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Standby Current in
Deep Power Down Mode
IDD7 See p.24~25
Speed
Unit Note
H
180 mA 1
1.0 mA
0.7 mA
30
mA
14
10
mA
10
50
mA
50
240 mA 1
360 mA
See Next
Page
mA
2
140 uA
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. See the tables of next page for more specific IDD6 current values.
Rev. 0.1 / Feb. 2004
20