HMT325U7CFR8A Datasheet, PDF (5/52 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered DIMMs Based on 2Gb C-Die

Pin Descriptions
Pin Name
Description
Pin Name
Description
A0–A15
BA0–BA2
RAS
CAS
WE
S0–S1
CKE0–CKE1
ODT0–ODT1
DQ0–DQ63
CB0–CB7
DQS0–DQS8
DQS0–DQS8
DM0–DM8
CK0–CK1
CK0–CK1
SDRAM address bus
SDRAM bank select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
DIMM Rank Select Lines
SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
DIMM ECC check bits
SDRAM data strobes
(positive line of differential pair)
SDRAM data strobes
(negative line of differential pair)
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
SCL
SDA
SA0–SA2
VDD*
VDDQ_*
VREFDQ
VREFCA
VSS
VDDSPD
NC
TEST
RESET
VTT
RSVD
-
I²C serial bus clock for EEPROM
I²C serial bus data line for EEPROM
I²C slave address select for EEPROM
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
SDRAM command/address reference
supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare pins (no connect)
Memory bus analysis tools
(unused on memory DIMMS)
Set DRAMs to Known State
SDRAM I/O termination supply
Reserved for future use
-
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
Rev. 1.1 / Jul. 2013
5