HMT325U7CFR8A Datasheet, PDF (34/52 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered DIMMs Based on 2Gb C-Die

DDR3L-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read command to
first data
t_AA
ACT to internal read or write
delay time
t_RCD
PRE command period
t_RP
ACT to ACT or REF command
period
t_RC
DDR3L-1333H
min
13.5
(13.125)^5,9
13.5
(13.125)^5,9
13.5
(13.125)^5,9
49.5
(49.125)^5,9
9-9-9
max
20
—
—
—
ACT to PRE command period t_RAS
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 7
CWL = 6
t_CK(AVG)
CL = 8
CL = 9
CL = 10
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5, 6
CWL = 7
CWL = 5, 6
CWL = 7
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
36
9 * tREFI
2.5
3.3
Reserved
Reserved
Reserved
1.875
< 2.5
(Optional)^5,9
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
1.5
<1.875
Reserved
1.5
<1.875
Reserved
6, (7), 8, 9, (10)
5, 6, 7
Unit
Note
ns
ns
ns
ns
ns
ns
1, 2, 3, 7
ns
1, 2, 3, 4, 7
ns
4
ns
4
ns
1, 2, 3, 4, 7
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 7
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3
ns
n_CK
n_CK
Rev. 1.1 / Jul. 2013
34